We've described the Core 2 architecture back in March. The Core 2 microarchitecture gives us some clues as to why performance might be better. Conroe is a four-wide architecture, so can issue four instructions per clock, as opposed to the three-wide used in NetBurst and Athlon 64 architectures. The Core 2 will also contain a full 128-bit wide SSE (Streaming SIMD (single instruction, multiple data) Extensions) engine that can execute one SIMD instruction per clock. The Extreme and higher-end mainstream desktop CPUs will offer 4MB of shared L2 cache. Finally, the use of micro-ops and macro-ops fusion, which can combine certain types of instructions as they come into the pipeline, enhances performance.

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